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K61P256M120SF3_1210 Datasheet, PDF (18/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family | |||
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General
⢠FlexBus clock = 50 MHz
⢠Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol Description
Min.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
â
300
μs
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
⢠VLLS1 â RUN
â
160
μs
⢠VLLS2 â RUN
â
114
μs
⢠VLLS3 â RUN
â
114
μs
⢠LLS â RUN
â
5.0
μs
⢠VLPS â RUN
â
5
μs
⢠STOP â RUN
â
4.8
μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
Notes
1
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Run mode current â all peripheral clocks
disabled, code executing from flash
⢠@ 1.8V
⢠@ 3.0V
Min.
â
Typ.
Max.
Unit
â
See note
mA
â
51.1
160
mA
â
51.7
162
mA
IDD_RUN
Run mode current â all peripheral clocks
enabled, code executing from flash
⢠@ 1.8V
⢠@ 3.0V
â
75.2
175
mA
â
75.9
177
mA
IDD_WAIT Wait mode high frequency current at 3.0 V â all
â
35.7
60
mA
peripheral clocks disabled
IDD_WAIT Wait mode reduced frequency current at 3.0 V â
â
19.6
44
mA
all peripheral clocks disabled
Table continues on the next page...
Notes
1
2
3
2
4
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
18
Freescale Semiconductor, Inc.
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