K61P256M120SF3_1210 Datasheet, PDF (17/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Table 4. Voltage and current operating behaviors (continued)
Symbol
I_{OLT_DDR}
Description
Output low current total for DDR pins
• DDR1
• DDR2
• LPDDR
Min.
Max.
Unit
—
100
mA
56
mA
39
mA
V_{OL_Tamper}
Output low voltage — high drive strength
• 2.7 V ≤ V_BAT ≤ 3.6 V, I_OL = 10mA
• 1.71 V ≤ V_BAT ≤ 2.7 V, I_OL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ V_BAT ≤ 3.6 V, I_OL = 2mA
• 1.71 V ≤ V_BAT ≤ 2.7 V, I_OL = 0.6mA
I_{OL_Tamper}
I_IN
I_IN
I_{IN_DDR}
I_{IN_DDR}
I_{IN_Tamper}
I_{IN_Tamper}
I_OZ
I_{OZ_DDR}
I_{OZ_Tamper}
R_PU
R_PD
R_ODT
Output low current total for Tamper pins
Input leakage current (per pin) for full temperature
range
Input leakage current (per pin) at 25°C
Input leakage current (per DDR pin) for full
temperature range
Input leakage current (per DDR pin) at 25°C
Input leakage current (per Tamper pin) for full
temperature range
Input leakage current (per Tamper pin) at 25°C
Hi-Z (off-state) leakage current (per pin)
Hi-Z (off-state) leakage current (per DDR pin)
Hi-Z (off-state) leakage current (per Tamper pin)
Internal pullup resistors (except Tamper pins)
Internal pulldown resistors (except Tamper pins)
On-die termination (ODT) resistance for DDR2
• R_tt1(eff) - 75 Ω
• R_tt2(eff) - 150 Ω
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
—
100
mA
—
1
μA
—
0.025
μA
—
1
μA
—
0.025
μA
—
1
μA
—
0.025
μA
—
1
μA
—
1
μA
—
1
μA
20
50
kΩ
20
50
kΩ
60
90
Ω
120
180
Ω
1. Measured at VDD=3.6V
2. Measured at V_DD supply voltage = V_DD min and Vinput = V_SS
3. Measured at V_DD supply voltage = V_DD min and Vinput = V_DD
General
Notes
1
1
2
3
5.2.4 Power mode transition operating behaviors
All specifications except t_POR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = FEI 100 MHz
• Bus clock = 50 MHz
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
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