K61P256M120SF3_1210 Datasheet, PDF (57/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

6.6.1.4
Peripheral operating requirements and behaviors
16-bit ADC with PGA characteristics
Table 32. 16-bit ADC with PGA characteristics
Symbol Description
I_{DDA_PGA} Supply current
I_{DC_PGA} Input DC current
Conditions
Low power
(ADC_PGA[PGALPb]=0)
Min.
Typ.¹
Max.
Unit
—
420
644
μA
A
Notes
2
3
G
Gain⁴
BW
PSRR
Input signal
bandwidth
Power supply
rejection ratio
Gain =1, V_REFPGA=1.2V,
V_CM=0.5V
Gain =64, V_REFPGA=1.2V,
V_CM=0.1V
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
• 16-bit modes
• < 16-bit modes
Gain=1
—
1.54
—
0.57
0.95
1
1.9
2
3.8
4
7.6
8
15.2
16
30.0
31.6
58.8
63.3
—
—
—
—
—
-84
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
—
-84
—
-85
V_OFS
Input offset
voltage
T_GSW
dG/dT
Gain switching
settling time
Gain drift over full
temperature range
dG/dV_DDA Gain drift over
supply voltage
• Chopping disabled
—
2.4
(ADC_PGA[PGACHPb]
=1)
—
0.2
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
—
—
• Gain=1
• Gain=64
• Gain=1
• Gain=64
—
6
—
31
—
0.07
—
0.14
Table continues on the next page...
—
—
1.05
2.1
4.2
8.4
16.6
33.2
67.8
4
40
—
—
—
—
—
μA
μA
R_AS < 100Ω
kHz
kHz
dB
V_DDA= 3V
±100mV,
f_VDDA= 50Hz,
60Hz
dB
V_CM=
dB
500mVpp,
f_VCM= 50Hz,
100Hz
mV Output offset =
V_OFS*(Gain+1)
mV
10
µs
5
10
42
0.21
0.31
ppm/°C
ppm/°C
%/V
%/V
V_DDA from 1.71
to 3.6V
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
57