K61P256M120SF3_1210 Datasheet, PDF (43/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

which are defined as:
Peripheral operating requirements and behaviors
T _NFC = T _L + T _H =
T _{input clock}
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER ⁼
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means T_H = T_L. In case the reciprocal of SCALER is not an integer:
T _L = (1 + SCALER / 2) x
T _NFC
2
T _H = (1 – SCALER / 2) x
T _NFC
2
For example, if SCALER is 0.2, then T_H = T_L = T_NFC/2.
T_NFC
T_H T_L
However, if SCALER is 0.667, then T_L = 2/3 x T_NFC and T_H = 1/3 x T_NFC.
T_NFC
T_H T_L
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 25. NFC specifications
Num
t_CLS
t_CLH
t_CS
t_CH
t_WP
t_ALS
Description
Min.
NFC_CLE setup time
NFC_CLE hold time
NFC_CEn setup time
NFC_CEn hold time
NFC_WP pulse width
NFC_ALE setup time
2T_H + T_L – 1
T_H + T_L – 1
2T_H + T_L – 1
T_H + T_L
T_L – 1
2T_H + T_L
Table continues on the next page...
Max.
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Freescale Semiconductor, Inc.
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Unit
ns
ns
ns
ns
ns
ns
43