K61P256M120SF3_1210 Datasheet, PDF (48/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Figure 19. DDR read timing, DQ vs. DQS
6.4.5 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num
FB1
FB2
FB3
FB4
FB5
Description
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Min.
2.7
—
20
—
0.5
8.5
0.5
Max.
3.6
FB_CLK
—
11.5
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
Notes
1
1
2
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num
FB1
FB2
FB3
Description
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Min.
1.71
—
1/FB_CLK
—
0
Max.
3.6
FB_CLK
—
13.5
—
Unit
V
MHz
ns
ns
ns
Notes
1
1
Table continues on the next page...
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
48
Freescale Semiconductor, Inc.