K61P256M120SF3_1210 Datasheet, PDF (30/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
TCLK (input)
J2
J3
J3
J4
J4
Figure 6. Test clock input timing
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 7. Boundary scan (JTAG) timing
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
30
Freescale Semiconductor, Inc.