K61P256M120SF3_1210 Datasheet, PDF (42/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 24. EzPort switching specifications (continued)
Num
EP1
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Description
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
—
—
2 x t_{EZP_CK}
5
5
2
5
—
0
—
Max.
f_SYS/2
f_SYS/8
—
—
—
—
—
16
—
12
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 11. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• T_H is the flash clock high time and
• T_L is flash clock low time,
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
42
Freescale Semiconductor, Inc.