K61P256M120SF3_1210 Datasheet, PDF (28/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 12. Debug trace operating behaviors (continued)
Symbol
T_wh
T_r
T_f
T_s
T_h
Description
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
Data hold
Min.
Max.
Unit
2
—
ns
—
3
ns
—
3
ns
3
—
ns
2
—
ns
Figure 4. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
2.7
0
0
0
Max.
3.6
10
25
50
Unit
V
MHz
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
ns
50
—
ns
20
—
ns
10
—
ns
Table continues on the next page...
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
28
Freescale Semiconductor, Inc.