K61P256M120SF3_1210 Datasheet, PDF (52/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 29. 16-bit ADC operating conditions (continued)
Symbol
C_rate
C_rate
Description
ADC conversion
rate
ADC conversion
rate
Conditions
≤ 13 bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
Min.
20.000
37.037
Typ.¹
Max.
Unit
—
818.330
Ksps
—
461.467
Ksps
Notes
5
5
1. Typical values assume V_DDA = 3.0 V, Temp = 25 °C, f_ADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The R_AS/C_AS
time constant should be kept to < 1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
Z_AS
R_AS
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
Z_ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
R_ADIN
ADC SAR
ENGINE
V_ADIN
V_AS
C_AS
INPUT PIN
INPUT PIN
INPUT PIN
R_ADIN
R_ADIN
R_ADIN
C_ADIN
Figure 22. ADC input impedance equivalency diagram
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
52
Freescale Semiconductor, Inc.