K61P256M120SF3_1210 Datasheet, PDF (76/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 37. I2S/SAI timing — master modes
Table 52. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
S11
S12
S13
S14
S15
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
Min.
2.7
80
45%
4.5
2
—
—
Max.
3.6
—
55%
—
—
21
15
Unit
V
ns
MCLK period
ns
ns
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid¹ —
25
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
76
Freescale Semiconductor, Inc.