K61P256M120SF3_1210 Datasheet, PDF (46/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 26. DDR controller — AC timing specifications
Symbol
Description
Frequency of operation
• DDR1
• DDR2
• LPDDR
Min.
83.3
125¹
50
Max.
150
150
150
t_DDRCK
Clock period
• DDR1
• DDR2
• LPDDR
6.6
12
6.6
8
6.6
20
V_OX-AC
t_DDRCKH
t_DDRCKL
t_CMV
t_CMH
t_DQSS
t_QS
t_QH
t_DQSQ
DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR
Pulse width high
Pulse width low
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output valid
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output hold
DQS rising edge to CK rising edge
Data and data mask output setup (DQ→DQS)
relative to DQS (DDR write mode)
Data and data mask output hold (DQS→DQ)
relative to DQS (DDR write mode)
DQS-DQ skew for DQS and associated DQ
signals
0.5 x V_{DD_DDR} 0.5 x V_{DD_DDR}
– 0.2 V
+ 0.2 V
0.5 x V_{DD_DDR} 0.5 x V_{DD_DDR}
– 0.125 V
+ 0.125 V
0.4 x V_{DD_DDR} 0.4 x V_{DD_DDR}
0.45
0.55
0.45
0.55
0.5 x t_DDRCK –
—
1
0.5 x t_DDRCK –
—
1
0.2 x t_DDRCK
0.25 x t_DDRCK –
1
0.2 x t_DDRCK
—
0.25 x t_DDRCK –
—
1
– (0.25 x
t_DDRCK – 1)
0.25 x t_DDRCK –
1
Unit
MHz
MHz
MHz
ns
ns
ns
V
V
V
t_DDRCK
t_DDRCK
ns
ns
ns
ns
ns
ns
Notes
2
3
3
4
5, 6
7
8
1. This is minimum frequency of operation according to JEDEC DDR2 specification.
2. DDR data rate = 2 x DDR clock frequency
3. Pulse width high plus pulse width low cannot exceed min and max clock period.
4. Command output valid should be 1/2 the memory bus clock (t_DDRCK) plus some minor adjustments for process,
temperature, and voltage variations.
5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
46
Freescale Semiconductor, Inc.