K61P256M120SF3_1210 Datasheet, PDF (69/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

6.8.5 ULPI timing specifications
Peripheral operating requirements and behaviors
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin
Interface. Control and data timing requirements for the ULPI pins are given in the
following table. These timings apply to synchronous mode only. All timings are
measured with respect to the clock as seen at the USB_CLKIN pin.
Table 44. ULPI timing specifications
Num
U1
U2
U3
U4
U5
Description
USB_CLKIN
operating
frequency
USB_CLKIN duty
cycle
USB_CLKIN clock
period
Input setup (control
and data)
Input hold (control
and data)
Output valid
(control and data)
Output hold (control
and data)
Min.
—
—
—
5
1
—
1
Typ.
60
50
16.67
—
—
—
—
Max.
—
—
—
—
—
9.5
—
Unit
MHz
%
ns
ns
ns
ns
ns
USB_CLKIN
U2
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
ULPI_STP
(control output)
ULPI_DATAn (output)
U1
U3
U4
U5
Figure 31. ULPI timing diagram
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
69