K61P256M120SF3_1210 Datasheet, PDF (45/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

NFC_CEn
NFC_WE
NFC_IOn
tCS
tWC
tWP tWH
tDS tDH
data
data
Peripheral operating requirements and behaviors
tCH
data
Figure 14. Write data latch cycle timing
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 15. Read data latch cycle timing in non-fast mode
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 16. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
45