K61P256M120SF3_1210 Datasheet, PDF (54/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 30. 16-bit ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA) (continued)
Symbol Description
Conditions¹
Min.
Typ.²
Max.
Unit
Notes
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
7
82
95
—
dB
16-bit single-ended mode
• Avg = 32
E_IL
Input leakage
error
V_TEMP25
Temp sensor
slope
Temp sensor
voltage
Across the full temperature
range of the device
25 °C
78
90
—
I_In × R_AS
—
1.715
—
—
719
—
dB
mV
mV/°C
I_In =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
mV
1. All accuracy numbers assume the ADC is calibrated with V_REFH = V_DDA
2. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (V_REFH - V_REFL)/2^N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
54
Freescale Semiconductor, Inc.