K61P256M120SF3_1210 Datasheet, PDF (77/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S11
S12
S12
S15
S13
S19
S15
S17
S16
S18
Peripheral operating requirements and behaviors
S16
S14
S15
S16
Figure 38. I2S/SAI timing — slave modes
6.8.12.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 53. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Characteristic
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
Min.
1.71
40
45%
80
45%
—
-1.0
—
0
20.5
0
Max.
3.6
—
55%
—
55%
15
—
15
—
—
—
Unit
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
77