MC7457RX1267LC Datasheet, PDF (8/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Features
— Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
• Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
• Power and thermal management
— 1.3-V processor core
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and back to nap using a QREQ/QACK processor-system handshake protocol.
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed on exiting the deep sleep
state.
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an
MPC7457-specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power consumption
• Performance monitor can be used to help debug system designs and improve software efficiency
• In-system testability and debugging features through JTAG boundary-scan capability
• Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
• Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
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Freescale Semiconductor