MC7457RX1267LC Datasheet, PDF (59/71 Pages) Freescale Semiconductor, Inc – Microprocessor

System Design Information
From Target
Board Sources
(if any)
SRESET
HRESET
QACK
HRESET
13
SRESET
11
SRESET
HRESET
0Ω⁵
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV_DD
OV_DD
OV_DD
OV_DD
12
34
56
78
9 10
11 12
13
KEY
No Pin
15 16
COP Connector
Physical Pin Out
TRST
4
6 ^VDD_SENSE
5¹
CHKSTP_OUT
15
Key
14 ²
CHKSTP_IN
8
TMS
9
TDO
1
TDI
3
TCK
7
QACK
2
10 NC
12 ⁶
16
TRST
2 kΩ ^{10 kΩ}
10 kΩ
10 kΩ
OV_DD
OV_DD
CHKSTP_OUT
OV_DD
OV_DD
CHKSTP_IN
TMS
TDO
TDI
TCK
QACK
2 kΩ ³
10 kΩ ⁴
OV_DD
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect
pin 5 of the COP header to OV_DD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an
additional GND pin for improved signal integrity.
Figure 26. JTAG Interface Connection
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
59