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MC7457RX1267LC Datasheet, PDF (5/71 Pages) Freescale Semiconductor, Inc – Microprocessor | |||
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Features
â Four integer units (IUs) that share 32 GPRs for integer operands
â Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions
â IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions
â Five-stage FPU and a 32-entry FPR file
â Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations
â Supports non-IEEE mode for time-critical operations
â Hardware support for denormalized numbers
â Thirty-two 64-bit FPRs for single- or double-precision operands
â Four vector units and 32-entry vector register file (VRs)
â Vector permute unit (VPU)
â Vector integer unit 1 (VIU1) handles short-latency AltiVec⢠integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws)
â Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm)
â Vector floating-point unit (VFPU)
â Three-stage load/store unit (LSU)
â Supports integer, floating-point, and vector instruction load/store traffic
â Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
â Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
throughput
â Four-cycle FPR load latency (single, double) with one-cycle throughput
â No additional delay for misaligned access within double-word boundary
â Dedicated adder calculates effective addresses (EAs)
â Supports store gathering
â Performs alignment, normalization, and precision conversion for floating-point data
â Executes cache control and TLB instructions
â Performs alignment, zero padding, and sign extension for integer data
â Supports hits under misses (multiple outstanding misses)
â Supports both big- and little-endian modes, including misaligned little-endian accesses
⢠Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
â Instructions can be dispatched only from the three lowest IQ entriesâIQ0, IQ1, and IQ2
â A maximum of three instructions can be dispatched to the issue queues per clock cycle
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
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