MC7457RX1267LC Datasheet, PDF (31/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Electrical and Thermal Characteristics
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Revisions and L3 I/O
Voltage Modes
Min
Max
Unit Notes
L3_CLK rise and fall time
t_L3CR, t_L3CF
—
0.75
ns
1, 2
Setup times: Data and parity
t_L3DVEH
0.1
—
ns
2, 3
Input hold times: Data and parity
t_L3DXEH
0.7
—
ns
2, 3
Valid times: Data and parity
t_L3CHDV
—
2.5
ns
2, 4, 5
Valid times: All other outputs
t_L3CHOV
—
1.8
ns
5
Output hold times: Data and parity
t_L3CHDX
1.4
—
ns
2, 4, 5
Output hold times: All other outputs
t_L3CHOX
1.0
—
ns
2, 5
L3_CLK to high impedance: Data and parity
t_L3CHDZ
—
3.0
ns
2
L3_CLK to high impedance: All other outputs
t_L3CHOZ
—
3.0
ns
2
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV_DD.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 10).
5. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for more
information.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
31