MC7457RX1267LC Datasheet, PDF (33/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Electrical and Thermal Characteristics
Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.
Outputs
L3_CLK[0,1]
VM
L3_ECHO_CLK[1,3]
t_L3CHOV
VM
t_L3CHOX
ADDR, L3_CNTL
t_L3CHDV
L3DATA WRITE
Inputs
t_L3CHOZ
t_L3CHDX
t_L3CHDZ
L3_ECHO_CLK[0,2]
Parity Inputs
L3 Data and Data
VM
t_L3DVEH
t_L3DXEH
VM = Midpoint Voltage (GV_DD/2)
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
5.2.5 IEEE 1149.1 AC Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through
Figure 17.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) ¹
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit Notes
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST assert time
Input setup times:
Boundary-scan data
TMS, TDI
Input hold times:
Boundary-scan data
TMS, TDI
f_TCLK
0
t_TCLK
30
t_JHJL
15
t_JR and t_JF
0
t_TRST
25
t_DVJH
4
t_IVJH
0
t_DXJH
20
t_IXJH
25
33.3
MHz
—
ns
—
ns
2
ns
—
ns
2
ns
3
—
—
ns
3
—
—
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
33