MC7457RX1267LC Datasheet, PDF (30/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.
Outputs
L3_CLK[0,1]
ADDR, L3CNTL
VM
t_L3CHOV
VM
VM
VM
VM
t_L3CHOZ
t_L3CHOX
L3DATA WRITE
t_L3CHDV
t_L3CLDV
t_L3CLDZ
t_L3CHDX
t_L3CLDX
Note: t_L3CHDV and t_L3CLDV as drawn here will be negative numbers, that is, output valid time will be
time before the clock edge.
Inputs
L3_ECHO_CLK[0,1,2,3]
VM
VM
VM
VM
VM
L3 Data and Data
Parity Inputs
t_L3DVEH
t_L3DXEH
t_L3DVEL
t_L3DXEL
Note: t_L3DVEH and t_L3DVEL as drawn here are negative numbers, that is, input setup time is
time after the clock edge.
VM = Midpoint Voltage (GV_DD/2)
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
5.2.4.3 L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7457 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the MPC7457 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2
are phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data
on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
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Freescale Semiconductor