MC7457RX1267LC Datasheet, PDF (50/71 Pages) Freescale Semiconductor, Inc – Microprocessor

System Design Information
9 System Design Information
This section provides system and thermal design recommendations for successful application of the
MPC7457.
9.1 Clocks
The following sections provide more detailed information regarding the clocking of the MPC7457.
9.1.1 Core Clocks and PLL Configuration
The MPC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency,
the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL
configuration for the MPC7457 is shown in Table 18 for a set of example frequencies. In this example,
shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies
that do not comply with the 1-GHz column in Table 8. Note that these configurations were different in
some earlier MPC7450-family devices and care should be taken when upgrading to the MPC7457 to verify
the correct PLL settings for an application.
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts
PLL_CFG[0:4]
01000
Bus-to- Core-to-
Core
VCO
Multiplier Multiplier
2x
2x
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
167
MHz
10000
3x
2x
10100
10110
10010
11010
01010
00100
00010
11000
01100
4x
2x
5x
2x
5.5x
2x
6x
2x
6.5x
2x
7x
2x
7.5x
2x
8x
2x
8.5x
2x
600
(1200)
638
(1276)
623
(1245)
664
(1328)
706
(1412)
600
(1200)
650
(1300)
700
(1400)
750
(1500)
800
(1600)
850
(1700)
667
(1333)
733
(1466)
800
(1600)
866
(1730)
931
(1862)
1000
(2000)
1064
(2128)
1131
(2261)
667
(1333)
835
(1670)
919
(1837)
1002
(2004)
1086
(2171)
1169
(2338)
1253
(2505)
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
50
Freescale Semiconductor