MC7457RX1267LC Datasheet, PDF (7/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Features
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— L2 cache supports parity and generation checking on both tags and data
• Level 3 (L3) cache interface (not implemented on MPC7447)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space
— Support for 1- or 2-MB of cache space
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1-MB) or 128-byte (2-MB) sectored line size
— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total
of 1-, 2-, or 4-MB of private memory
— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined
synchronous burst SRAMs, and pipelined (register-register) late write synchronous burst
SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
• Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm
– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is
performed in hardware or by system software)
• Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data
cache and L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
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