MC7457RX1267LC Datasheet, PDF (34/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Electrical and Thermal Characteristics
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) ¹ (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit Notes
Valid times:
Boundary-scan data
TDO
t_JLDV
4
t_JLOV
4
ns
4
20
25
Output hold times:
Boundary-scan data
TDO
t_JLDX
30
t_JLOX
30
ns
4
—
—
TCK to output high impedance:
Boundary-scan data
TDO
t_JLDZ
3
t_JLOZ
3
ns
4, 5
19
9
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 13).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.
Output
Z₀ = 50 Ω
R_L = 50 Ω
OV_DD/2
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
TCLK
VM
VM
VM
t_JHJL
t_JR
t_JF
t_TCLK
VM = Midpoint Voltage (OV_DD/2)
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
TRST
VM
VM
t_TRST
VM = Midpoint Voltage (OV_DD/2)
Figure 15. TRST Timing Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
34
Freescale Semiconductor