MC7457RX1267LC Datasheet, PDF (13/71 Pages) Freescale Semiconductor, Inc – Microprocessor

OV_DD/GV_DD + 20%
OV_DD/GV_DD + 5%
OV_DD/GV_DD
V_IH
Electrical and Thermal Characteristics
V_IL
GND
GND – 0.3 V
GND – 0.7 V
Not to exceed 10%
of t_SYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7457 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see
Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied
to the OV_DD or GV_DD power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input Threshold
is Relative to:
L3VSEL Signal ¹
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
2, 3
¬HRESET
Not Available
¬HRESET
1.5 V
2, 4
HRESET
2.5 V
HRESET
2.5 V
2
1
2.5 V
1
2.5 V
2
Notes:
1. Not implemented on MPC7447.
2. Caution: The input threshold selection must agree with the OV_DD/GV_DD voltages supplied. See notes in Table 2.
3. If used, pull-down resistors should be less than 250 Ω.
4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
13