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MC7457RX1267LC Datasheet, PDF (6/71 Pages) Freescale Semiconductor, Inc – Microprocessor | |||
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Features
â Space must be available in the CQ for an instruction to dispatch (this includes instructions that
are assigned a space in the CQ but not in an issue queue)
⢠Rename buffers
â 16 GPR rename buffers
â 16 FPR rename buffers
â 16 VR rename buffers
⢠Dispatch unit
â Decode/dispatch stage fully decodes each instruction
⢠Completion unit
â The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
â Guarantees sequential programming model (precise exception model)
â Monitors all dispatched instructions and retires them in order
â Tracks unresolved branches and flushes instructions after a mispredicted branch
â Retires as many as three instructions per clock cycle
⢠Separate on-chip L1 instruction and data caches (Harvard architecture)
â 32-Kbyte, eight-way set associative instruction and data caches
â Pseudo least recently used (PLRU) replacement algorithm
â 32-byte (eight-word) L1 cache block
â Physically indexed/physical tags
â Cache write-back or write-through operation programmable on a per-page or per-block basis
â Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
â Caches can be disabled in software.
â Caches can be locked in software.
â MESI data cache coherency maintained in hardware
â Separate copy of data cache tags for efficient snooping
â L1 cache supports parity generation and checking
â No snooping of instruction cache except for icbi instruction
â Data cache supports AltiVec LRU and transient instructions
â Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
⢠Level 2 (L2) cache interface
â On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache
â Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
â A total nine-cycle load latency for an L1 data cache miss that hits in L2
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
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Freescale Semiconductor
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