MC7457RX1267LC Datasheet, PDF (52/71 Pages) Freescale Semiconductor, Inc – Microprocessor

System Design Information
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)
PLL_CFG[0:4]
Bus-to- Core-to-
Core
VCO
Multiplier Multiplier
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
167
MHz
11110
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 5.2.1, “Clock AC
Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However,
the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at
one-half the frequency of SYSCLK and offset in phase to meet the required input setup t_IVKH and hold time t_IXKH (see
Table 9). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at
SYSCLK frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
9.1.2 L3 Clocks
The MPC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7457. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7457 core, and timing analysis of the circuit
board routing. Table 19 shows various example L3 clock frequencies that can be obtained for a given set
of core frequencies.
Table 19. Sample Core-to-L3 Frequencies ¹
Core
Frequency ÷2 ÷2.5 ÷3 ÷3.5 ÷4 ÷4.5 ÷5 ÷5.5 ÷6 ÷6.5 ÷7 ÷7.5 ÷8
(MHz) ²
500
533
550
600
650
666
700
733
800
866
933
1000
250 200 167 143 125 111 100 91
83
77
71
67
63
266 213 178 152 133 118 107 97
89
82
76
71
67
275 220 183 157 138 122 110 100 92
85
79
73
69
300 240 200 171 150 133 120 109 100 92
86
80
75
325 260 217 186 163 144 130 118 108 100 93
87
81
333 266 222 190 167 148 133 121 111 102 95
89
83
350 280 233 200 175 156 140 127 117 108 100 93
88
367 293 244 209 183 163 147 133 122 113 105 98
92
400 320 266 230 200 178 160 145 133 123 114 107 100
433 347 289 248 217 192 173 157 145 133 124 115 108
467 373 311 266 233 207 187 170 156 144 133 124 117
500 400 333 285 250 222 200 182 166 154 143 133 125
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
52
Freescale Semiconductor