MC7457RX1267LC Datasheet, PDF(23/71 Page) Freescale Semiconductor, Inc

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MC7457RX1267LC Datasheet, PDF (23/71 Pages) Freescale Semiconductor, Inc – Microprocessor

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Electrical and Thermal Characteristics

Table 10. L3_CLK Output AC Timing Specifications (continued)

At recommended operating conditions. See Table 4.

Device Revision (L3 I/O Voltage) 6

Parameter

Symbol

Rev 1.1. (All I/O Modes)

Rev 1.2

Rev 1.2 (1.5-V I/O Mode) (1.8-, 2.5-V I/O Modes)

Unit

Notes

Min Typ Max Min Typ Max

L3 clock jitter

â Â± 75 â

â Â± 75 ps

Notes:

1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 5.2.3, âL3 Clock

AC Specifications,â for an explanation that this maximum frequency is not functionally tested at speed by Freescale. The

minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals which

are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or

Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch

data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data, and

control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the

L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage

noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3

timing analysis.

6. L3 I/O voltage mode must be configured by L3VSEL as described in Table 3, and voltage supplied at GVDD must match

mode selected as specified in Table 4. See Table 22 for revision level information and part marking.

The L3_CLK timing diagram is shown in Figure 7.

L3_CLK0

tL3_CLK

tCHCL

tL3CR

tL3CF

L3_CLK1

For PB2 or Late Write:

tL3CSKW1

L3_ECHO_CLK1

L3_ECHO_CLK3

Figure 7. L3_CLK_OUT Output Timing Diagram

tL3CSKW2

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

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