MC7457RX1267LC Datasheet, PDF (32/71 Pages) Freescale Semiconductor, Inc – Microprocessor

Electrical and Thermal Characteristics
Figure 11 shows the typical connection diagram for the MPC7457 interfaced to PB2 SRAMs or Late Write
SRAMs.
MPC7457
Denotes
Receive (SRAM
to MPC7457)
Aligned Signals
Denotes
Transmit
(MPC7457 to
SRAM)
Aligned Signals
L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
L3_ECHO_CLK[0]
{L3_DATA[0:15], L3_DP[0:1]}
L3_CLK[0]
{L3_DATA[16:31], L3_DP[2:3]}
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
SRAM 0
SA[16:0]
SS
SW
DQ[0:17] _ZZ GND
K
DQ[18:36]
G GND
K ^GVDD^{/2 1}
SRAM 1
SA[16:0]
SS
SW
{L3_DATA[32:47], L3_DP[4:5]}
L3_CLK[1]
{L3_DATA[48:63], L3_DP[6:7]}
L3_ECHO_CLK[3]
DQ[0:17]
K
ZZ GND
G GND
DQ[18:36] K _GVDD/2 ¹
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
32
Freescale Semiconductor