33889 Datasheet, PDF (56/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33889 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
33889DW
33889EG
28-PIN
SOICW
Packaging and Thermal Considerations
The MC33889 is offered in a 28 pin SOICW, single die package. There is a
single heat source (P), a single junction temperature (T_J), and thermal resistance
(R_θJA).
T_J = _RθJA . _P
DWB SUFFIX
EG SUFFIX (PB-FREE)
98ASB42345
28-PIN SOICW
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
NOTE FOR PACKAGE DIMENSIONS,
REFER TO THE 33889 DEVICE DATASHEET.
Standards
Table 34. Thermal Performance Comparison
Thermal Resistance
[°C/W]
Ρ_θJA ^{(1) (2)}
42
Ρ_θJB ^{(2) (3)}
11
Ρ_θJA ^{(1) (4)}
69
Ρ_θϑΧ ⁽⁵⁾
23
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
4. Single layer thermal test board per JEDEC JESD51-3.
5. Thermal resistance between the die junction and the
package top surface; cold plate attached to the package top
surface and remaining surfaces insulated.
20 Terminal SOICW
1.27 mm Pitch
18.0 mm x 7.5 mm Body
Figure 23. Surface Mount for SOIC Wide Body
Non-Exposed Pad
33889
56
Analog Integrated Circuit Device Data
Freescale Semiconductor