33889 Datasheet, PDF (25/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MASTER IN/SLAVE OUT (MISO
MISO is the Master In Slave Out pin of the serial peripheral
interface. Data is sent from the SBC to the microcontroller
through the MISO pin.
MASTER OUT/SLAVE IN (MOSI)
MOSI is the Master Out Slave In pin of the serial peripheral
interface. Control data from a microcontroller is received
through this pin.
CHIP SELECT (CS)
CS is the Chip Select pin of the serial peripheral interface.
When this pin is LOW, the SPI port of the device is selected.
WATCH DOG (WDOG)
The Watchdog output pin is asserted LOW to flag that the
software watchdog has not been properly triggered.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
DEVICE SUPPLY
The device is supplied from the battery line through the
VSUP pin. An external diode is required to protect against
negative transients and reverse battery. It can operate from
4.5 V and under the jump start condition at 27 V DC. This pin
sustains standard automotive voltage conditions such as
load dump at 40 V. When V_SUP falls below 3.0 V typical, the
MC33889 detects it and stores the information in the SPI
register, in a bit called “BATFAIL”. This detection is available
in all operation modes.
VDD1 VOLTAGE REGULATOR
VDD1 Regulator is a 5.0 V output voltage with total current
capability of 200 mA. It includes a voltage monitoring circuitry
associated with a reset function. The VDD1 regulator is fully
protected against overcurrent, short-circuit and has
overtemperature detection warning flags and shutdown with
hysteresis.
HS1 VBAT SWITCH OUTPUT
HS1 output is a 2.0 ohm typical switch from the VSUP pin.
It allows the supply of external switches and their associated
pullup or pull-down circuitry, for example, in conjunction with
the wake-up input pins. Output current is limited to 200 mA
and HS1 is protected against short-circuit and has an over
temperature shutdown (reported into the IOR register). The
HS1 output is controlled from the internal register and the
SPI. It can be activated at regular intervals in sleep mode
thanks to an internal timer. It can also be permanently turned
on in normal or stand-by modes to drive external loads, such
as relays or supply peripheral components. In case of
inductive load drive, external clamp circuitry must be added.
SPI
The complete device control as well as the status report is
done through an 8 bit SPI interface. Refer to the SPI
paragraph.
V2 REGULATOR
V2 Regulator circuitry is designed to drive an external path
transistor in order to increase output current flexibility. Two
pins are used: V2 and V2CTRL. Output voltage is 5.0 V and
is realized by a tracking function of the VDD1 regulator. A
recommended ballast transistor is the MJD32C. Other
transistors might be used, however depending upon the PNP
gain, an external resistor capacitor network might be
connected between the emitter and base of the PNP. The use
of external ballast is optional (refer to simplified typical
application). The state of V2 is reported into the IOR register
(if V2 is below 4.5 V typical, or in cases of overload or short-
circuit).
CAN
The device incorporates a low speed fault tolerant CAN
physical interface. The speed rate is up to 125 kBauds.
The state of the CAN interface is programmable through
the SPI. Reference the CAN transceiver description on page
30.
PACKAGE AND THERMAL CONSIDERATION
The device is proposed in a standard surface mount SO28
package. In order to improve the thermal performances of the
SO28 package, 8 pins are internally connected to the lead
frame and are used for heat transfer to the printed circuit
board.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33889
25