33889 Datasheet, PDF (50/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 29. Cyclic Sense Timing
CSP2
0
0
0
0
1
1
1
1
CSP1
0
0
1
1
0
0
1
1
CSP0
0
1
0
1
0
1
0
1
Cyclic sense timing [ms]
5
10
20
40
75
100
200
400
Cyclic sense on time
Cyclic sense timing
10 µs to 20 µs
HS1
Sample
t
LPC REGISTER
Description: This register controls:
- The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic)
- Enable or Disable the forced wake-up function (SBC automatic wake-up after time spend in sleep or stop mode, time defined
by TIM2 register)
- Enable or disable the sense of the wake-up inputs (LX) at sampling point of the cyclic sense period (LX2HS1 bit).
Table 30. LPC Register
LPC
D3
D2
D1
D0
$110b
W
LX2HS1
FWU
IDDS
HS1AUTO
R
Reset
0
0
0
0
Reset condition
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
33889
50
Analog Integrated Circuit Device Data
Freescale Semiconductor