33889 Datasheet, PDF (40/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO _{A2 A1 A0 R/W D3 D2 D1 D0}
MOSI
Read operation: R/W bit = 0
Write operation: R/W bit = 1
address
data
Figure 20. Data Format Description
The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register address, bit 4 is a read/write bit. The last 4 bits
are data send from MCU to SBC or read back from SBC to MCU.
During write operation state of MISO has no signification.
During read operation only the last 4 bits at MISO have a meaning (content of the accessed register)
Following tables describe the SPI register list, and register bit meaning.
Registers “reset value” is also described, as well as the “reset condition”. reset condition is the condition which cause the bit
to be set at the “reset value”.
Possible reset condition are:
Power On Reset: POR
SBC mode transition:
NR2R - Normal Request to Reset mode
NR2N - Normal Request to Normal mode
N2R - Normal to Reset mode
STB2R - Standby to Reset mode
STO2R - Stop to Reset mode
SBC mode:RESET - SBC in Reset mode
33889
40
Analog Integrated Circuit Device Data
Freescale Semiconductor