33889 Datasheet, PDF (48/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 24. Status bits
L0WUb
0
1
0
L0WUa
0
1
1
FDIS bit in CAN
register
Description
0
No wake-up occurred at L0 (sleep or stop mode).
Low level state on L0 (standby or normal mode)
0
Wake-up occurred at L0 (sleep or stop mode).
High level state on L0 (standby or normal mode)
1
Wake-up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set
to xx00 before sleep or stop mode.
L1WUb
0
1
L1WUa
0
1
Description
No wake-up occurred at L1 (sleep or stop mode).
Low level state on L1 (standby or normal mode)
Wake-up occurred at L1 (sleep or stop mode).
High level state on L1 (standby or normal mode)
TIM REGISTERS
Description: This register is split into 2 sub registers, TIM1 and TIM2.
TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.
TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1.
No read operation is allowed for registers TIM1 and TIM2
TIM REGISTER
Table 25. TIM Register.
TIM1
D3
D2
D1
D0
$101b
W
0
WDW
WDT1
WDT0
R
Reset
0
0
0
Reset condition
POR, RESET
POR, RESET
POR, RESET
33889
48
Analog Integrated Circuit Device Data
Freescale Semiconductor