33889 Datasheet, PDF (29/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Step 5) Write to the MCR register normal debug (0001
x101), stand-by debug (0001 x110), or Stop debug (0001
x111)
While in debug mode, the SBC can be used without
having to clear the W/D on a regular basis to facilitate
software and hardware debugging.
Step 6) To leave the debug mode, write 0000 to the MCR
register.
To avoid entering the debug mode after a power up, first
read the BATFAIL bit (MCR read) and write 0000 into the
MCR.
Figure 11 illustrates entering the debug mode.
VSUP
VDD1
BATFAIL
TIM1(step 3)
MCR (step5)
SPI
MCR(step4)
SPI: read batfail
MCR (step6)
debug mode
SBC in debug Mode, no W/D ^{SBC not in debug Mode and W/D on}
Figure 11. Debug Mode Enter
MCU FLASH PROGRAMMING CONFIGURATION
To facilitate the possibility of down loading software into
the application memory (MCU EEPROM or Flash), the SBC
allows the following capabilities: The VDD1 can be forced by
an external power supply to 5.0 V and the reset and WDOG
output by external signal sources to zero or 5.0 V without
damage. This supplies the complete application board with
external power supply and applies the correct signal to the
reset pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33889
29