33889 Datasheet, PDF (28/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CAN WAKE-UP
The device can wake-up from a CAN message. A CAN
wake-up cannot be disabled.
SPI WAKE-UP
The device can wake-up by the CS pin in sleep or stop
mode. Wake-up is detected by the CS pin transition from a
low to high level. In stop mode this correspond to the
condition where the MCU and SBC are both in Stop mode,
and when the application wake-up events come through the
MCU.
SYSTEM POWER UP
At power up the device automatically wakes up.
DEVICE POWER UP, SBC WAKE UP
After device or system power up or a wake-up from sleep
mode, the SBC enters into “reset mode” then into “normal
request mode”.
BATTERY FALL EARLY WARNING
This function provides an interrupt when the VSUP
voltage is below the 6.1 V typical. This interrupt is maskable.
A hysteresis is included. Operation is only in Normal and
Stand-by modes. VBAT low state reports in the IOR register.
RESET AND WDOG OPERATION
The following figure shows the reset and watchdog output
operations. Reset is active at device power up and wake-up.
Reset is activated in case the VDD1 falls or the watchdog is
not triggered. The WDOG output is active low as soon as the
reset goes low and stays low for as long as the watchdog is
not properly re-activated by the SPI.
The WDOG output pin is a push pull structure than can
drive external components of the application, for instance to
signal the MCU is in a wrong operation. Even if it is internally
turned on (low-state), the reset pin can be forced to 5.0 V at
25°C only, thanks to its internally limited current drive
capability. The WDOG stays low until the Watchdog register
is properly addressed through the SPI.
VDD1
RESET
WDOG
SPI
W/D clear
SPI CS
Watchdog timeout
Watchdog
period
Watchdog register addressed
Figure 10. Reset and WDOG Function Diagram
DEBUG MODE APPLICATION HARDWARE AND
SOFTWARE DEBUG WITH THE SBC.
When the SBC is mounted on the same printed circuit
board as the micro controller, it supplies both application
software and the SBC with a dedicated routine that must be
debugged. The following features allow the user to debug the
software by disabling the SBC internal software watchdog
timer.
DEVICE POWER UP, RESET PIN CONNECTED TO VDD1
At SBC power up, the VDD1 voltage is provided, but if no
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debugging
and avoid an MCU reset, the Reset pin can be connected
directly to VDD1 by a jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY
DEBUG AND STOP DEBUG)
The software watchdog can be disabled through the SPI.
In order to avoid unwanted watchdog disables, and to limit the
risk of disabling the watchdog during an SBC normal
operation, the watchdog disable has to be performed with the
following sequence:
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the
SBC enters normal request mode)
Step 3) Write to the TIM1 register to allow the SBC to enter
Normal mode
Step 4) Write to the MCR register with data 0000 (this
enables the debug mode). (Complete SPI byte: 000 1 0000)
33889
28
Analog Integrated Circuit Device Data
Freescale Semiconductor