33889 Datasheet, PDF (27/60 Pages) Freescale Semiconductor, Inc – System Basis Chip with Low Speed Fault Tolerant CAN Interface

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the
device after a wake-up event from sleep or stop mode, or
after device power up. In this mode, the VDD1 regulator is
ON, V2 is off, and the reset pin is high. As soon as the device
enters the normal request mode, an internal 350 ms timer is
started. During these 350 ms, the microcontroller of the
application must address the SBC via the SPI and configure
the watchdog register (TIM1 register). This is the condition for
the SBC to leave the Normal request Mode and enter the
Normal mode, and to set the watchdog timer according to the
configuration done during the Normal Request mode.
The “BATFAIL flag” is a bit which is triggered when V_SUP
falls below 3.0 V. This bit is set into the MCR register. It is
reset by the MCR register read.
INTERNAL CLOCK
This device has an internal clock used to generate all
timings (reset, watchdog, cyclic wake-up, filtering time
etc....).
RESET PIN
A reset output is available in order to reset the
microcontroller. Reset causes are:
• V_DD1 falling out of range: if V_DD1 falls below the reset
threshold (parameter R_ST-TH), the reset pin is pulled low
until V_DD1 returns to the nominal voltage.
• Power on reset: at device power on or at device wake-up
from sleep mode, the reset is maintained low until V_DD1 is
within its operation range.
• Watchdog timeout: if the watchdog is not cleared, the SBC
will pull the reset pin low for the duration of the reset
duration time (parameter: RESET-DUR).
For debug purposes at 25°C, the reset pin can be shorted
to 5.0 V.
SOFTWARE WATCHDOG (SELECTABLE WINDOW OR
TIMEOUT WATCHDOG)
The software watchdog is used in the SBC normal and
stand-by modes for monitoring the MCU. The watchdog can
be either a window or timeout. This is selectable by the SPI
(register TIM, bit WDW). Default is the window watchdog.
The period of the watchdog is selectable by the SPI from 5.0
to 350 ms (register TIM, bits WDT0 and WDT1). When the
window watchdog is selected, the closed window is the first
half of the selected period, and the open window is the
second half of the period. The watchdog can only be cleared
within the open window time. An attempt to clear the
watchdog in the closed window will generate a reset. The
Watchdog is cleared through the SPI by addressing the TIM
register.
Refer to ”table for reset pin operations” operation in mode
2.
WAKE-UP CAPABILITIES
Several wake-up capabilities are available for the device
when it is in sleep or stop mode. When a wake-up has
occurred, the wake-up event is stored into the WUR or CAN
registers. The MCU can then access the wake-up source.
The wake-up options are selectable through the SPI while the
device is in normal or standby mode, and prior to entering low
power mode (sleep or stop mode).
WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT
CYCLIC SENSE
The wake-up lines are dedicated to sense external switch
states, and when changes occur to wake-up the MCU (In
sleep or stop modes). The wake-up pins are able to handle
40 V DC. The internal threshold is 3.0 V typical, and these
inputs can be used as an input port expander. The wake-up
inputs state can be read through the SPI (register WUR). L0
has a lower threshold than L1 in order to allow a connection
and wake-up from a digital output such as a CAN physical
interface.
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND
WAKE-UP INPUTS L0, L1)
The SBC can wake-up from a state change of one of the
wake-up input lines (L0, L1), while the external pullup or
pulldown resistor of the switches associated to the wake-up
input lines are biased with HS1 VSUP switch. The HS1 switch
is activated in sleep or stop mode from an internal timer.
Cyclic sense and forced wake-up are exclusive. If Cyclic
sense is enabled, the forced wake-up can not be enabled.
INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION
In case the Cyclic sense and Lx both level sensitive
conditions are use together, the initial value for Lx inputs are
sampled in two cases:
1) When the register LPC[D3 and D0] are set and
2) At cyclic sense event, that is when device is in sleep or
stop mode and HS1 is active.
The consequence is that when the device wake up by Lx
transition, the new value is sampled as default, then when the
device is set back into low power again, it will automatically
wake up.
The user should reset the LPC bits [D3 and D0] to 0 and
set them again to the desired value prior to enter sleep or
stop mode.
FORCED WAKE-UP
The SBC can wake-up automatically after a
predetermined time spent in sleep or stop mode. Forced
wake-up is enabled by setting bit FWU in the LPC register.
Cyclic sense and forced wake-up are exclusive. If forced
wake-up is enabled, the Cyclic sense can not be enabled.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33889
27