XR88C681_06 Datasheet, PDF (77/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
MR2n[3:0] - Stop Bit Length
This bit field programs the duration of the stop bits
appended to each transmitted character. Stop bit
duration of 9/16 to 1 bit time and 1 9/16 to 2 bit times, in
increments of 1/16 bits can be programmed for character
lengths of 6, 7 and 8 bits. For a 5 bit character, the stop bit
duration can be programmed from 1-1/16 to 2 bit times.
If an external 1x clock is programmed for the transmitter
clock (TXCn), MR2n[3] = 0 selects a stop bit duration of
one bit time and MR2n[3] = 1 selects a duration of two bit
times for transmission.
The receiver only checks for mark condition at the center
of the first stop bit (that is, one bit time after the last data or
parity bit is sampled) regardless of the programmed
transmitted stop bit length. If the receiver does not sample
a “mark” a “Frame Error” (FE) is flagged in the Status
Register.
Bit 7
Received
Break
0 = No
1 = Yes
Bit 6
Bit 5
Framing Error Parity Error
0 = No
1 = Yes
0 = No
1 = Yes
Bit 4
Overrun
Error
0 = No
1 = Yes
G.4 Status Register, SRn
The Status Register provides the user with status on the
RHR and THR (Receiver and Transmitter FIFOs,
respectively); and serves to provide the CPU with a
measure of the quality of the reception of data by the
receiver. FIFO Status indicators are useful in polled
systems and allows the CPU to check and see if the
Transmitter is empty and/or is ready for data from the
CPU. The FIFO Status indicators also indicate whether or
not the RHR has a character, which is waiting to be read
by the CPU, or is full and incapable of receiving any more
characters without an overrun. The Transmitter and
Receiver FIFO status indicators are located in the lower
nibble of the Status Register.
The upper nibble of the Status Register alerts the user of
any data reception errors. The bit-format of the Status
Register and a discussion of each bit follows:
Bit 3
TXEMT
Bit 2
TXRDY
Bit 1
FFULL
Bit 0
RXRDY
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
Table 28. Status Register - SRA, SRB
SRn[7] Received Break
This bit indicates that an all zero character of the
programmed character length was received without a
stop bit. Only a single FIFO position is occupied when a
break is received. Additional transfers into the FIFO are
inhibited until the RXD line returns to the marking state for
at least half a bit time. This is defined as two successive
edges of the internal or external 1x clock.
When this bit is set, the channel’s “CHANGE IN BREAK
STATUS” bit in the ISR is set. The bit in the ISR is also set
when the end of the break condition, as defined above, is
detected.
The chip’s break detect logic can detect breaks that begin
in the middle of a character. However, the break must
persist until the end of the next character time in order for it
to be detected.
If the Error Mode, of the channel, has been set to
“Character” Mode, this bit only applies to the Character at
the top of the RHR. This bit will be cleared if the RXDn
input is brought to a logic “high” level, in the next
character.
If the “Error” Mode has been set to “Block” mode, then this
bit, once set will remain asserted until the “RESET
ERROR STATUS” command has been invoked (please
see Table 3). Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[6] Framing Error
Following reception of the character bits, and any
associated parity bit, the Receiver will check for a “mark”
condition one bit-time following the last data or parity bit.
This “mark” condition is the STOP bit. If the Receiver
does not detect a “mark” at this time, the bit is toggled
“high” flagging the occurrence of a Frame Error (FE).
If the Error Mode has been set to “Character” Mode, this
bit only applies to the Character at the top of the RHR. If
Rev. 2.11
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