XR88C681_06 Datasheet, PDF (43/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Clock input
GND
+5V
PHI
A0 - A15
D0 - D7
-INT
-NMI
-WAIT
-BUSRQ
-HALT
-RFSH
-BUSAK
-WR
-RD
-MREQ
-IORQ
-M1
-RESET
Figure 18. Schematic of Z-80 CPU Module
-MEMW
-MEMR
-IOW
-IOR
-INTA
Z-80 CPU Interrupt Servicing Capability
The Z-80 CPU contains two interrupt request pins: -NMI
and -INT. -NMI is the “Non-Maskable” interrupt request
input pin; and -INT is the “Maskable” interrupt request
input pin. For the sake of interfacing to the DUART, we are
only concerned with the -INT pin.
The Z-80 CPU can be configured to operate in one of
three different interrupt modes:
D External Vectored
D Direct
D “Peripheral” Vectored
Each of these interrupt modes use the -INT pin of the Z-80
CPU and will be discussed in the following sections.
External Vectored Interrupt Processing (Interrupt
Mode 0)
The Z-80 P will operate in this interrupt mode if the “IM 0”
instruction has been executed. Whenever the -INT pin is
asserted by a peripheral device requesting an interrupt,
the CPU will complete its current instruction. After
completion of this instruction, the CPU module will assert
-INTA (toggle “low”). -INTA is the active-low “Interrupt
Acknowledge” signal that the CPU module outputs in
order to initiate the process of interrupt servicing. When
the Z-80 CPU operates in the Interrupt Mode 0, it is
Rev. 2.11
43