XR88C681_06 Datasheet, PDF (30/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
U1
INTE
INT
DBIN
8080A CPU
D0
D1
D2
D3
D4
D5
D6
D7
Vcc
U5
U6
U2
8228
Bi-Directional
BUS Driver
INTA
V_cc
U3
-OE1 -OE2
DO0
DI0
DO1
DI1
DO2
DI2
DO3
DI3
DO4
DI4
DO5
DI5
DO6
DI6
DO7
DI7
SN74LS244
U4
-INTR
XR88C681
DUART
Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART
to the 8080A CPU, for “External” Vectored Interrupt Processing
(Interrupt Service Routine resides at 0020₁₆ in Memory)
Since the 8080A CPU can support up to 8 different RST
instructions, it can support up to 8 different
interrupt-driven peripheral devices. This can be achieved
by replicating the approach, presented in Figure 7, and
by hardwiring the op-codes for each of the RESTART
instructions to the inputs of the Data Buffers (see
Table 10).
These Data Buffers should be enabled only during the
-INTA cycle, and only when their associated peripheral
requested the interrupt service.
C.6.1.3 8085 Microprocessor
The 8085 CPU is another early Intel microprocessor,
although it is more advanced than the 8080A CPU. Some
of the advancements that were made in the transition
from the 8080A to the 8085 include combining the Clock
Generator functions of the 8224 onto the CPU chip,
adding a non-maskable interrupt request, adding 3
“direct” interrupt request input pins, and adding some
form of interrupt priority. The 8085 still requires some glue
logic in order to produce the Control Bus signals (i.e.,
-IOR, -IOW, -MEMR, -MEMW). Further, in order to
minimize pin count, the 8085 contains a multiplexed
Address/Data Bus (AD0 - AD7). Specifically, the lower 8
bits of the Address Bus share pins with the 8 bit Data Bus.
Hence, a 74LS373 8-bit latch is needed in order to
demultiplex the Address and Data buses.
Rev. 2.11
30