XR88C681_06 Datasheet, PDF (76/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
RXCn
Incoming ^RXDn
Serial Data
Receive Shift Register
Receive Holding
Register
TXCn
Transmit Shift Register
TXDn
Outgoing
Serial Data
Transmit Holding
Register
Note: The CPU has no access to the Serial Data during Remote Loopback Mode.
Figure 41. A Block Diagram Depicting Remote Loopback Mode
In this mode:
1. Received data is transmitted on the channel’s TXDn
output
2. Received data is not sent to the CPU and the error
status conditions are not checked.
3. Parity and framing (stop bits) are transmitted as
received.
4. The receiver must be enabled.
5. The received break is echoed as received until the
next valid start bit is detected.
MR2n[5] - Transmitter Request-to-Send Control
Ordinarily, the RTS (Request to Send) output is asserted
or negated by invoking the “SET OUTPUT PORT BITS
COMMAND” or “CLEAR OUTPUT PORT BITS
COMMAND” in the appropriate manner, by the system
software. However, setting MR2n[5] = 1 allows the
Channel Transmitter to negate RTS automatically, one bit
time after the characters in the TSR and THR have been
transmitted and are now empty.
Figure 44 presents a diagram illustrate how a
Transmitter-Controlled Request-to-Send configuration
would function.
MR2n[4] - Clear to Send Control
If this bit is a 0, the channels -CTSn input (IP0 for Channel
A, or IP1 for Channel B) has no effect on the transmitter. If
the bit is a “1”, the transmitter will check the state of its
-CTSn input each time is it ready to send a character. If
-CTSn is low (or “true”), the character is transmitted. If
-CTSn is high (or negated), TXDn remains in the marking
state and the transmission of the next character is
delayed until -CTSn goes low. Changes in the -CTSn
input while a character is being serialized do not affect
transmission of that character. This phenomenon is
further illustrated in Figure 42 and Figure 44.
Rev. 2.11
76