XR88C681_06 Datasheet, PDF (58/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock
Figure 30 shows that the phase relationship between the Receiver’s sampling point and each serial data bit is changing.
In this case, the Receiver is sampling each serial data bit, earlier and earlier in the bit period, with each successive data
bit. This phenomenon is known as receiver drift. If there is no correction for receiver drift, there will be many errors in the
transmission and reception of this serial data, as depicted in Figure 31.
Received Data
0
1
0
1
0
0
1
0
1
Actual Data
0
1
0
1
0
1
0
1
Figure 31. Illustration of an Error due to Receiver Drift
Figure 31 shows the Receiver sampling an eight bit string of data with bit pattern 0101010. It is interesting to note that, in
Figure 31, the Receiver sampled 01010010. It should be noted that Receiver drift can also be a problem is the local
Receiver is slower than the remote Transmitter clock.
Rev. 2.11
58