XR88C681_06 Datasheet, PDF (32/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
AD0 - AD7
X1
X2
ALE
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
-INTA
A8 - A15
-IO/M
-RD
-WR
8085 CPU
1D - 8D
1Q - 8Q
C
74LS373
-MEMR
-MEMW
D0 - D7
A0 - A3
A0 - A3
A4 - A7
-CS_DUART
-CS
A8 - A15
Address
Decoder
-RD
-WR
XR88C681
-CS_OTHER_IC
Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped).
The DUART’s -INTR pin was deliberately omitted from
Figure 9, because its use will be addressed in Figure 10
and Figure 11.
8085 CPU Module Interrupt Structure
The 8085 CPU supports both Direct and “External”
Vectored Interrupt processing. The 8085 has 4 maskable
interrupt request inputs (RST 5.5, RST 6.5, RTS 7.5, and
INTR), and 1 non-maskable interrupt request input
(TRAP). When discussing interfacing for the interrupt
servicing of peripheral devices such as the DUART, we
are only concerned with the maskable interrupt request
inputs. Of the four maskable interrupt request inputs;
three of these inputs support “Direct Interrupt”
processing. The remaining one interrupt request
supports “External Vectored Interrupt” processing.
Table 11 lists these Interrupt Request inputs and their
characteristics/features.
Rev. 2.11
32