XR88C681_06 Datasheet, PDF (13/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
SYSTEM DESCRIPTION
The XR88C681 consists of two independent, full-duplex
communication channels; each consisting of their own
Transmitter and Receiver. Each channel of the DUART
may be independently programmed for operating mode
and data format. The DUART can interface to a wide
range of processors with a minimal amount of
components. The operating speed of each receiver and
transmitter may be selected from one of 23 internally
generated fixed bit rates, from a clock derived from an
internal counter/timer, or from an externally supplied 1x or
16x clock. The bit rate generator (the source of the 23
different fixed bit rates) can operate directly from a crystal
connected across two pins or from an external clock. The
ability to independently program the operating speed of
the receiver and transmitter of each channel makes the
DUART attractive for split speed channel applications
such as clustered terminal systems.
Receiver data is quadrupled buffered and the transmitter
data is dual-buffered via on-chip FIFOs in order to
minimize the risk of receiver overrun and to reduce
overhead in interrupt driven applications. The DUART
also provides a flow control capability to inhibit
transmission from a remote device when the buffer of the
receiving DUART is full, thus preventing loss of data.
The DUART also provides a general purpose 16 bit
counter/timer (which may also be used as programmable
bit rate generators), a 7 bit multi-purpose input port and an
8 bit multi-purpose output port (for the 40 pin DIP and 44
pin PLCC packages only).
PRINCIPLES OF OPERATION
Figure 1 presents an overall block diagram of the DUART.
As illustrated in the block diagram, the DUART consists of
the following major functional blocks:
D Data Bus Buffer
D Interrupt Control
D Input Port
D Serial Communication Channels A and B
D Operation Control
D Timing Control
D Output Port
A. DATA BUS BUFFER
The data bus buffer provides the interface between the
internal (within the chip) and external data buses. It is
controlled by the operation control block to allow data
transfers to take place between the host CPU and the
DUART.
B. OPERATION CONTROL BLOCK
The control logic of the Operation Control block receives
operating commands from the CPU and generates proper
signals to the various sections of the DUART. The
Operation Control Block functions as the user interface to
the rest of the device. Specifically, it is responsible for
DUART Register Address Decoding, and Command
Decoding. Therefore all commands to set baud rates,
parity, other communication protocol parameters, start or
stop the Counter/Timer or reading a “status register” to
monitor data communication performance must go
through the Operation Control Block.
The Operation Control Block will control DUART
performance based upon the following input signals.
Address Inputs, A0 - A3
-RD
-WR
-CS
RESET
When using the 6800 family processor, the DUART will
require some glue logic. Interfacing a 6800 Family
Processor to the DUART can be easily achieved by
including a small amount of external logic devices, as
depicted in Figure 2.
Rev. 2.11
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