XR88C681_06 Datasheet, PDF (70/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Incoming ^RXDn
Serial Data
Receive Shift Register
Receiver Clock (from Timing Block)
RXCn
To Data Bus
To be read by the CPU
Receive Holding
Register
Figure 37. A Simplified Drawing of the Receiver Shift Register
and Receiver Holding Register
The receiver functions by sensing the voltage level at the
RXDn input. When the far-end transmitter is idle, its TXDn
output (and consequently, the RXDn input) is
continuously “marking”. During this period the Receiver is
inactive and is not receiving or processing any data.
However, when the far-end transmitter sends the START
bit, (with its TXDn output toggling “low”), a receiver clock,
which is 16 times the baud rate (with the 16x clock), will
start sampling this START bit. If the receiver determines
that its RXDn input is still “low” after its 7th sample, then
the receiver hardware considers this signal to be a valid
START bit. If the RXDn input is not “low” at the 7th
sample, the Receiver will ignore this downward pulse as
“noise”. From this 7th sample on, the Receiver will
sample each successive bit at one bit-period intervals
(1/baud rate) with the 1x clock. The purpose of this 16x
Clock is then two-fold.
1. To verify that the detected “low” level in the RXDn input
is indeed a START bit.
2. To establish the phase relationship between the 1x bit
sampling clock, and the incoming serial data stream.
The idea is to sample each data bit in the middle of its
bit period.
Please note that if a 16X clock is selected for the receiver,
this over-sampling procedure occurs with each and every
start bit.
The receiver will continue to sample (and receive) each
bit of the character that follows the START bit, at one-bit
time intervals. Upon reception of the character’s MSB the
receiver will check parity (if programmed) or will sample
for the STOP bit. If the Receiver samples a mark
condition at this time and the parity check (if any) was
valid; a successful reception of the character is
presumed; and the Receiver will prepare to sense and
oversample the occurrence of the START bit for the next
character.
Rev. 2.11
70