XR88C681_06 Datasheet, PDF (47/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
(e.g., AD0 - AD15 becomes D0 - D15, A16/S3 - A19/S6
becomes S3 - S6). A second group of multiplexed pins is
controlled by the MN/-MX input pin. When this pin is high,
the “min” mode is selected and pins 24 through 31 take on
the control definitions shown under the MN/-MX = 1
column in Table 14. When the 8086 P operates in this
mode, it presents a control bus very similar to that of the
8085 P, and requires only an address latch and a clock
generator to form a CPU module.
Pin Number
24
25
26
27
28
29
30
31
MN/-MX = 1 (Min Mode)
HOLD
HLDA
-WR
M/-IO
DT/R
-DEN
ALE
-INTA
MN/-MX = 0 (Max Mode)
-RQ/-GT0
-RQ/-GT1
-LOCK
-S2
-S1
-S0
QS0
QS1
Table 14. MN/-MX Mode and Function of Pins 24-31 of 8086 CPU Device.
When MN/-MX is low, the 8086 P is operating in the “max”
mode. This mode is intended for more complex
applications in which the 8086 P requires support from
the 8087 numeric data processor (NDP). In this mode, a
special bus controller (the 8288) is required to generate
the memory and I/O control bus signals.
The 8086 P contains two interrupt request inputs: INTR
and NMI. NMI is the active-high “non-maskable” interrupt
request input; and INTR is the “maskable” interrupt
request input. If the 8086 P is operating in the “min”
mode, then the -INTA (Interrupt Acknowledge) pin is
available on Pin 24 (see Figure 20). However, if the
8086 P is operating in the “max” mode, then the -INTA
signal must be derived from the -S0, -S1, and -S2 pins via
the 8288 bus controller. Table 15 presents the processor
status and 8288 active outputs based on the -S0, -S1, and
-S2 “max” mode status signals.
-S2
-S1
-S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Processor State
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
8288 Active Output
-INTA
-IORC
-IOWC
None
-MRDC
-MRDC
-MWTC
None
Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of -S0, -S1 and -S2
Rev. 2.11
47