XR88C681_06 Datasheet, PDF (53/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
D.2 Bit Rate Generator
The BRG (Bit Rate Generator) accepts the timing output
of the Oscillator Circuit and generate the clock signal for
23 commonly used data communication bit rates ranging
from 50 bps up to 115.2kbps. Please note that the BRG
will only generate these standard bit rates if the Oscillator
Circuit is running at 3.6864 MHz. Additionally, the actual
clock frequencies output from the BRG are at 16 times
these rates.
The user can select one of two different sets of bit rates, to
be generated from the BRG. This selection is made by
setting or clearing ACR[7]. A listing of these sets of Bit
Rates, from the BRG, is presented in the discussion of the
Clock Select Registers (CSRs) in Section D.5. A block
diagram of the BRG circuitry is presented in Figure 27.
X1/CLK
X2
Oscillator
Circuit
ACR[7]
Bit Rate Generator
Channels A and B
CSRA[7:4]
32:1 MUX
RXCA
CSRA[3:0]
32:1 MUX
TXCA
CSRB[7:4]
32:1 MUX
RXCB
CSRB[3:0]
32:1 MUX
TXCB
Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block
Rev. 2.11
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