XR88C681_06 Datasheet, PDF (26/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Port 3
Port 3 is a dual-purpose port on pins 10 - 17. In addition to functioning as general purpose I/O, these pins have multiple
functions. Each of these pins have an alternate purpose, as listed in Table 8.
Bit
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Name
RXD
TXD
-INT0
-INT1
T0
T1
-WR
-RD
Alternate Function
Receive Data for Serial Port
Transmit Data for Serial Port
External Interrupt 0
External Interrupt 1
Timer/Counter 0 External Input
Timer/Counter 1 External Input
External Data Memory Write Strobe
External Data Memory Read Strobe
Table 8. Alternate Functions of Port 3 Pins
The 8051 also has numerous additional pins which are
relevant to interfacing to the XR88C681 DUART or other
peripherals. These pins are:
Interrupt
-INT0
-INT1
Location
0003H
0013H
ALE - Address Latch Enable
If Port 0 is used in its alternate mode - as the data bus and
the lower byte of the address bus -- ALE is the signal that
latches the address into an external register during the
first half of a memory cycle. Once this is done, the Port 0
lines are then available for data input or output during the
second half of the memory cycle, when the data transfer
takes place.
-INT0 (P3.2) and -INT1 (P3.3)
-INT0 and -INT1 are external interrupt request inputs to
the 8051 C. Each of these interrupt pins support “direct
interrupt” processing. In this case, the term “direct”
means that if one of these inputs are asserted, then
program control will automatically branch to a specific
(fixed) location in code memory. This location is
determined by the circuit design of the 8051 C IC and
cannot be changed. Table 9 presents the location (in
code memory) that the program control will branch to, if
either of these inputs are asserted.
Table 9. Interrupt Service Routine locations (in
Code Memory) for -INT0 and -INT1
Therefore, if the user is using either one of these inputs as
an interrupt request input, then the user must insure that
the appropriate interrupt service routine or an
unconditional branch instruction (to the interrupt service
routine) is located at one of these address locations.
If the 8051 C is required to interface to external
components in the data memory space of sizes greater
than 256 bytes, then both Ports 0 and Port 2 must be used
as the address and data lines. Port 0 will function as a
multiplexed address/data bus. During the first half of a
memory cycle, Port 0 will operate as the lower address
byte. During the second half of the memory cycle Port 0
will operate as the bi-directional data bus. Port 2 will be
used as the upper address byte. ALE and the use of a
74LS373 transparent latch device can be used to
demultiplex the Address and Data bus signals.
Figure 5 presents a schematic illustrating how the
XR88C681 DUART can be interfaced to the 8051 C.
Rev. 2.11
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