XR88C681_06 Datasheet, PDF (42/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
Z-80 P can be configured to operate in one of three
different “interrupt modes”. The Z-80 is also a little bit less
complicated to interface to (than some of the P/ Cs
previously mentioned) because its address and data bus
are not multiplexed. Figure 17 presents a schematic of
the pin out of the Z-80 P.
A11 ₁
A12 2
A13 3
A14 4
A15 ₅
PHI 6
D4 7
D3 8
D5 9
D6 ₁₀
V_CC 11
D2 12
D7 13
D0 ₁₄
D1 15
-INT 16
-NMI 17
-HALT 18
-MREQ 19
-IORQ 20
Z80 CPU
40 A10
39 A9
38 _A8
37 A7
36 A6
35 A5
34 A4
33 _A3
32 A2
31 A1
30 A0
29 GND
28 -RFSH
27 -M1
26 -RESET
25 -BUSRQ
24 -WAIT
23 -BUSAK
22 -WR
21 -RD
Figure 17. Pin Out of the Z80 CPU Device
The Z-80 CPU will support Read/Write operations
between memory and I/O. The Z-80 does require some
additional glue logic in order to interface directly to
memory and peripheral devices. For instance, the Z-80
CPU device does not come with the control bus signals:
-MEMR (Memory Read), -MEMW (Memory Write), -IOR
(I/O Port Read), -IOW (I/O Port Write) or -IACK/-INTA
(Interrupt Acknowledge) pins. Each of these functions
can be derived from the -RD, -WR, -IORQ, -MREQ and
-M1 pins. Figure 18 presents a schematic of the Z-80
CPU Module, which shows how once can extract the
control bus signals from these CPU control pins.
Rev. 2.11
42