XR88C681_06 Datasheet, PDF (64/101 Pages) Exar Corporation – CMOS Dual Channel UART (DUART)

XR88C681
In order to enable the “Input Port Change of State” interrupt, one must do the following.
D Write the appropriate data to the lower nibble of ACR. The bit formats for ACR is presented in Table 23. Please
note that the applicable bits, within the ACR register, are shaded.
Bit 7
BRG Set
Select
0 = Set1
1 = Set2
Bit 6
Bit 5
Bit 4
Counter/Timer Mode and Source
See Table 7
Bit 3
Delta IP3
Interrupt
0 = OFF
1 = ON
Bit 2
Delta IP2
Interrupt
0 = OFF
1 = ON
Bit 1
Delta IP1
Interrupt
0 = OFF
1 = ON
Bit 0
Delta IP0
Interrupt
0 = OFF
1 = ON
Table 23. ACR- Auxiliary Control Register
D Setting IMR[7].
Note: This “two-tiered” interrupt enabling/disabling approach, for the “Input Change of State” interrupt allows tremendous flexibility
for the user. Setting or clearing the bits in ACR[3:0] allows the user to specify exactly which Input Port pins to be enabled (or
disabled) for generating the “Input Port Change of State” interrupt. Setting or clearing IMR[7] allows the user to “globally”
enable or disable this interrupt.
The upper nibble of the IPCR will indicate which of the four
input pins experienced the “Change of State.” The lower
nibble of the IPCR contains the present state of these
input pins. Therefore, when reading the IPCR, in
response to the “Change of State” interrupt, the CPU will
determine:
D The input pin(s) that toggled.
D The final state of the changing input pin.
E.3 28 Pin Packaged DUARTs
The 28 pin packaged DUARTs come with only one input
port pin, IP2. Therefore, the only alternative functions that
are available to the device (via this input port pin) are
CT_EX (C/T External Clock Input) and RXCB (External
Clock input for Receiver Channel B).
F. OUTPUT PORT
The DUART consists of an 8 bit parallel Output Port. The
Output Port can be used as a general purpose output or
can be used for output timing and status signals by
appropriately programming of the mode registers (MR1A,
B and MR2A, B) and also the output port configuration
register, OPCR. When used to output status signals the
Output Port pins are open drain, which allows their use in
a wire OR interrupt scheme.
Programming the Output Port is a little different from the
conventional writes to a typical parallel port or the data
bus. The Output Port circuitry consists of the Output Port
Register (OPR), and the output port pins themselves.
The contents of the OPR are complements of the actual
state of the Output Port pins.
For Example:
If the bit OPR[5] is set to a logic “1”, this will result in the
OP5 pin being at a logic “0”. Likewise, if the bit OPR[5] is
set to a logic “0”, this results in the OP5 pin being at a logic
“1”. The other thing that makes programming the parallel
port a little odd is the procedure that one must use to
accomplish this feat. When writing to this parallel output
port, one must invoke one of the two address triggered
commands: SET OUTPUT PORT BITS and CLEAR
OUTPUT PORT BITS. It is important to note that when
invoking the “SET OUTPUT PORT BITS” command, the
user is setting the bits (to logic “1”) in the OPR. However,
this action results in setting the corresponding Output
Port pins to logic “0”; due to the complementary
relationship between the state of the Output Port pins and
the bits in the OPR. Likewise, when the CLEAR OUTPUT
PORT BITS command is invoked, the specified bits,
within the OPR are “cleared” to logic “0”. However, the
corresponding Output Port pins are set to the logic “1”
state.
The state of each bit within the OPR, following a Power-on
Reset (POR), is all “0”. Therefore, the state of each
Output Port pin, following a POR is logic “1”.
The bits of the OPR can be set and cleared individually. A
bit is set by the address-triggered “SET OUTPUT PORT
BITS” command (see Table 1) with the accompanying
Rev. 2.11
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